Services & Pricing

The Complete Semiconductor Bundle · All 6 Packs

Job-Hunting Map + Interview Bank + four frontline process reports (SiN / low-k / CMOS / Diamond). Buy separately = ¥375; the bundle is ¥299 — save ¥76 and get the whole shelf at once.

• The Semiconductor Big-Company Job-Hunting Map (9 pages)
• Semiconductor Interview Question Bank (8 modules · ~50 Q&A)
• High-Tensile-Stress SiN Thin Film for 28nm CMOS (report)
• Advanced low-k / ULK Thin-Film Technology (report)
• CMOS Device Failure Effects & Advanced Process Modules (report)
• MPCVD Semiconductor-Grade Diamond Thin Film (42 pages)

Each pack includes a 1-page free sample — try before you buy.

🆕 New: "CVD Process Interview 50 Q&A" (¥29.9) and "APF Amorphous-Carbon Hard Mask Technical Report · Optimized & Expanded" (¥59) are now sold separately — see the Job Prep and Process Deep-Dive sections below.

🪐 Paired Knowledge Planet annual membership "Diamond半导体工艺圈": continuously updated library, auto-renew, searchable archives — join once, benefit long-term.

The Semiconductor Big-Company Job-Hunting Map (PDF, 9 pages)

Written by an 11-year front-line engineer for anyone wanting into semiconductors. Clarifies what insiders know but outsiders can't find: how domestic fabs are distributed, what core roles (CVD / device / PIE / YE / TD) really do, interview hot topics, salary ranges, and how to choose / prepare / avoid pitfalls. A map to read before sending résumés.

• Industry chain panorama: Fab / design / equipment / materials / OSAT / IDM
• 12 representative companies at a glance: HQ / business / process edge / fit
• 5 core roles dissected: real work + skills + interview points + background fit
• Salary ranges (fresh / 3-yr / 5-yr) + strategy + pitfall list + FAQ
• Message after payment for cloud-disk code, PDF kept forever

Semiconductor Interview Question Bank (PDF, 8 modules · ~50 questions)

High-frequency interview questions compiled by an 11-year engineer, covering the largest common denominator of technical interviews: process basics, CVD thin-film, CMOS device, PIE integration, yield (YE), reliability failure, EHS safety, behavioral. Each with answer + analysis — self-test and prep in one.

• 8 modules: process basics / CVD / CMOS / PIE / yield / reliability / EHS / behavioral
• ~50 questions: MCQs with answer + analysis, shorts with key points
• Front-line focused: stress engineering, low-k, STI, TDDB, NBTI, PID
• Message after payment for cloud-disk code, PDF kept forever

Semiconductor Q&A & Career Consulting — 6 questions, illustrated answers

11 years of front-line experience answering your specific questions. 6-question quota across two tracks: ① semiconductor tech (CVD thin-film / CMOS device / reliability / process integration); ② career planning (resume direction / job-hopping rhythm / technical path / PIE-YE transition). Each with illustrated breakdown, archive-friendly.

• 6 questions, under ¥7/question — volume pricing
• Tech: thin-film process / device physics / failure analysis / process window
• Career: job direction / hopping rhythm / tech route / role-switch advice
• Illustrated answers: principle sketch + text, clearer than words alone
• Delivered on WeChat, chat log reusable anytime

CVD Process Interview 50 Q&A · Deep-dive for thin-film process roles

A vertical interview question bank for CVD / thin-film process roles, compiled by an 11-year front-line CVD / PIE engineer. Not generic name-dropping — the 50 questions are split by real fab modules: fundamentals, equipment & process types (APCVD / LPCVD / PECVD / HDP / FCVD / ALD), dielectric films, metal CVD, defects & yield, and interview practice. Each question clarifies where the film lives (FEOL / BEOL), what it does, and where the pitfalls are — so you can speak with substance, not just keywords.

• 6 modules, 50 Q&A: from CVD principles to defect & yield
• Each question tagged FEOL / BEOL, clarifying the film's application
• Front-line focused: step coverage, stress, particles, uniformity, PID
• Interview talking points: turn project experience into highlights
• Message after payment for cloud-disk code, PDF kept forever

High-Tensile-Stress SiN Thin Film for 28nm CMOS Platforms

Systematic strain engineering for NMOS mobility: PECVD stress tuning, UV cure physics, dual-stress-layer / SMT integration, hot-carrier reliability trade-offs — plus a 28nm process-window quick-reference table. Based on open literature & production experience. ~13-page PDF.

• Both CESL and SMT NMOS enhancement routes covered
• UV cure physical model + cascaded-wavelength strategy
• Nitrogen-rich film vs. H-content reliability trade-off
• Ready to use as DOE baseline on your fab line

Advanced low-k / ULK Thin-Film Technology (Detailed)

Systematic low-k/ULK dielectric thin films: interconnect RC-delay bottleneck, Clausius-Mossotti k-reduction physics, FSG/CDO/porous-ULK families, precursor chemistry quick-reference, UV-cure strengthening, PID plasma damage & mitigation, and the core k ↔ strength ↔ reliability triangle. Based on open principles. 22 pages.

• FSG / CDO / porous-ULK families and technology nodes
• Clausius-Mossotti k-reduction physics + porosity effective-medium model
• Precursors (OMCTS / DEMS / BCHD / ATRP) chemistry quick-ref
• UV cure & PID mechanisms, usable as DOE reference on line

CMOS Device Failure Effects & Advanced Process Modules

For device-reliability, process-integration and PIE/YE engineers: systematic CMOS device failure effects and advanced process modules. Reliability: HCI, NBTI/PBTI, TDDB degradation mechanisms. Process: STI, well engineering, salicide, SMT, dual-stress liner, contact/metal and low-k interconnect principles & integration logic. Based on open principles. 39 pages.

• Four reliability effects: HCI / NBTI / PBTI / TDDB
• Advanced modules: STI · well engineering · salicide · SMT
• Interconnect & failure linkage: low-k, EM and device-process synergy
• Usable as reliability DOE reference on line

MPCVD Semiconductor-Grade Diamond Thin Film Research (42 pages)

Diamond — the "ultimate semiconductor": 5.47 eV bandgap, ~2200 W/mK room-temperature thermal conductivity (5× copper, 13× silicon), breakdown field and carrier mobility beating Si / GaN / SiC. As AI compute hits the "thermal wall" and high-power devices & quantum tech (NV centers) heat up, semiconductor-grade diamond is moving from lab to industry. This report covers MPCVD equipment & plasma principles, nucleation & homoepitaxy, doping (B p-type feasible, n-type still a world challenge) & defect control, quality characterization, and ties together AI-chip cooling, power devices and quantum sensing.

• MPCVD equipment & plasma process window (T / pressure / CH4 conc. / H2 etch)
• Nucleation, homoepitaxy & single-crystal diamond growth
• Doping & defect control: B p-type feasible, why n-type is still hard
• Semiconductor-grade quality: defects, resistivity & carrier concentration
• Hot topics: AI-chip cooling · power devices · NV-center quantum